Open Hardware Pulse

LLVM CIRCT published firtool 1.161.0 with a dense set of hardware-compiler changes. The release adds AXI4 cut and clock-domain-crossing operations, core SystemVerilog net and var type support, MOS switch primitive handling in ImportVerilog, FIRRTL optimizer preservation for register initial values, PyCDE type-alias fixes, and ESI channel updates.

CHIPS Alliance released Chisel 7.16.0 with HDL authoring and verification improvements. The release preserves literals in Cat, adds a basic reimplementation of chiseltest's verify function, fixes Scala 2 public constructor vals and DynamicContext leakage on exceptions, improves hardware connection diagnostics, and updates the bundled CIRCT dependency through firtool 1.160.0.

CHIPS Alliance published Caliptra firmware 2.1.3 as a combined runtime and FMC release. The notes add vendor-authorized debug artifact support, active debug-policy reporting in FW_INFO, Encryption Engine self-test plumbing, ML-KEM and OCP-LOCK API updates, OCP recovery-image tooling, FPGA external I3C host boot testing, and security fixes for AES-XTS key generation, mailbox key-usage checks, PL0 privilege checks, and PCR access.

Antmicro published a technical OpenROAD update on migrating global-placement acceleration from a CUDA-specific path toward a Kokkos-based implementation. The article explains how Kokkos execution and memory spaces improve backend portability, why determinism required some single-threaded tradeoffs, and how benchmark data on the ariane133 design still shows substantial runtime gains for the RTL-to-GDS flow.

Apache TVM published v0.27.0 with a large release-note set spanning AI compiler and runtime work. Highlights include shared-KV attention and PagedAttentionKVCache checkpoint primitives, TIRx CUDA/PTX updates through PTX ISA 9.4 and CUDA 13.4 target support, WebGPU and Web runtime improvements, LLVM 23 compatibility, Jetson AGX Thor target tagging, and many ONNX, PyTorch, Relax, DLight, and symbolic-shape fixes.

MLCommons introduced the first MLPerf Training LLM post-training benchmark, planned for the v6.1 submission round in October 2026. The benchmark uses RLVR on software-engineering tasks with Qwen 3.5 397B, R2E-Gym environments, OpenHands agent rollouts, pass@4 validation, and a reference implementation built around NeMo-RL, vLLM, Ray, and Apptainer sandboxes.

RISC-V International published a Monte Cimone v3 project snapshot for RISC-V high-performance computing. The post describes an SG2044-based cluster testbed evaluated with HPL and STREAM plus power measurements, reporting 3.08 GFLOPs/W, about 10x MCv1 energy efficiency, and peak-efficiency comparisons against Intel Sapphire Rapids and NVIDIA Grace CPU Superchip systems.

lowRISC published a secure-by-design analysis of how the European Cyber Resilience Act affects open silicon maintainers and downstream integrators. The post connects CRA obligations to OpenTitan, Ibex, CHERI-Mocha, COSMIC, GitHub security advisories, SBOM and HBOM work, and Eclipse Foundation Open Regulatory Compliance guidance.

FOSSi Foundation published El Correo Libre issue 100. The issue records ORConf 2026 as the largest ORConf yet, with almost 200 registered attendees, more than 60 presentations, and recordings on the FOSSi YouTube channel, and it also marks FuseSoC's fifteenth anniversary as an open-source package manager and build-flow tool for FPGA and ASIC projects.

RISC-V International published a five-question profile of Openchip's BER10 project. The article describes BER10 as a European RISC-V application processor that taped out in under two years, booted an operating system without requiring a respin, and combines a 64-bit Linux-capable processor, vector unit, coherent fabric, memory/interconnect subsystem, and management tile.

FOSSi Foundation published Krzysztof Bieganski's Verilator talk. The video abstract reports progress toward broader verification support, including experimental four-state logic, improved constrained-random stimulus generation, remaining UVM scheduling and bug-fix work, SVA nearing feature completeness, and coverage-tooling updates.

FOSSi Foundation published Rafael Medina Morillas's GVSoC talk. The abstract describes GVSoC as a configurable event-driven simulator for IoT processors and complex SoCs, using C++ models and Python configuration for faster prototyping, design exploration, full-platform many-core simulation, and integration with other simulators.

FOSSi Foundation published Frans Skarman's Spade HDL talk. The abstract shifts from language introduction to concrete projects built with Spade, including RISC-V cores, Ethernet and camera-stack work, and a pure-RTL UI library.

FOSSi Foundation published Olof Kindgren's FuseSoC and Edalize roadmap talk. The abstract frames FuseSoC as a widely used IP-management solution with a public core registry and describes Edalize as an EDA-flow manager supporting more than 50 tools, then outlines planned features for managing, building, simulating, and analyzing larger designs.

FOSSi Foundation published Maciej Dudek's talk on radiation hardening and fault injection. The abstract covers ongoing Triple Modular Redundancy work for the CHIPS Alliance VeeR-EL2 open-source RISC-V core and new open Verilator-based tooling used to inject faults and verify the VeeR-EL2 TMR configuration.

FOSSi Foundation published Andreas Wendleder's Borg talk. The official abstract describes a small RISC-V SoC driving a tile-based FP16 GPU, built end-to-end with libre tools including Chisel, Yosys, LibreLane/OpenROAD, Verilator, and Nix, and submitted as an ASIC tapeout while exposing and fixing upstream toolchain issues.

FOSSi Foundation published Daniel Arevalos' ShapeIC talk. The official abstract presents ShapeIC as an open-source project for fast analog integrated-circuit design-space exploration, using lookup-table characterization of devices and circuit primitives to reduce repeated full circuit simulation during hierarchical transistor sizing.

FOSSi Foundation published Tomasz Hemperek's SpiceBind talk. The official abstract frames SpiceBind as a project that connects ngspice to a VPI-capable HDL simulator, placing it in the growing open-source analog/mixed-signal verification stack alongside open PDKs, circuit simulators, design tools, and libraries.

FOSSi Foundation published Felix Arnold's Spire talk. The official abstract describes Spire as a Python-embedded HDL that lets designers express optimization intent in source code and apply transformations such as arithmetic architecture selection and fusion, FSM minimization, and ABC-backed logic optimization.

FOSSi Foundation published Vladimir Milovanovic's ORConf 2026 talk on RIVET, a Chisel-based Ethernet MAC generator for RISC-V systems. The talk and linked project materials describe multi-rate MAC interfaces, DMA, ARP, IPv4, UDP, TileLink, AXI4-Stream, cocotb/Verilator testing, and Chipyard-oriented integration for network-capable ASIC and FPGA prototypes.

FOSSi Foundation published Kaleb Barrett's coconext talk. The abstract describes coconext as an experimental cocotb fork and redesign intended to address performance by adding a first-class cocotb-like C++ API, preserving the existing Python cocotb API, and connecting the two through a low-friction binding layer for mixed-language testbenches, models, monitors, and drivers.

FOSSi Foundation published Stuart Alldred's Bucket update talk. The official abstract describes Bucket as an open-source Python project for collecting and viewing functional coverage, now maintained by Noodle-Bytes after Vypercore shut down, with updates including an improved viewer, cross-run coverage comparison, a new archive format, and adoption by additional silicon companies.

FOSSi Foundation published Martin Schoeberl's Doppio talk. The official abstract presents Doppio as an open-source, software-based verification framework that applies software-testing ideas and modern programming languages such as Java and Scala to digital-circuit verification, aiming to modernize verification practices rooted in older hardware-verification languages.

RISC-V architecture tests 4.1.0 is an official non-prerelease ACT release that expands architectural coverage and test generation. The release notes highlight added or improved privileged tests for Zawrs, Sstvala, Ssccptr, Zama16b, Zkr, exceptions, interrupts, PMP, and other areas, plus lower-privilege execution support and default Vx/Vls vector test generation on supported DUTs.

Antmicro announced Zephelin 1.0.0 for profiling Zephyr RTOS applications. The release adds live tracing from boards, unified delivery of instrumentation and tracing data over UART, GDB, or USB backends, Trace Viewer support for multiple flamegraphs across threads, runs, applications, and heterogeneous SoCs, plus VS Code integration for viewing captured traces.

YosysHQ released Yosys 0.69 with cleanup that affects synthesis scripts: legacy abc, coolrunner2, greenpak4, nlutmap, retiming, abc9, abc2, and logger stderr options were removed, while the Verific frontend gained a -sv2023 flag for SystemVerilog 2023 support.

Antmicro and Nuvoton announced collaboration around Nuvoton secure chips in the open-source Renode simulation framework. The article says the work builds on existing Renode support for Nuvoton's NPCR1 OpenTitan Earl Grey Based Secure MCU IC, a RISC-V Root of Trust platform with secure accelerators and SPI/I2C/UART/USB/GPIO interfaces, enabling early firmware development, testing, and debugging.

CHIPS Alliance published Caliptra runtime/FMC 1.3.0 with software support for PQC MLDSA. The release notes list PQC seed initialization, MLDSA signature verification, attestation for firmware downstream of Caliptra Core, and an update to the Rust 1.95 toolchain.

Antmicro described open-source power-analysis workflows built around OpenROAD, Verilator, trace2power, and OpenSTA. The workflows use VCD traces to report peak power by clock cycle, estimate glitch-related power from repeated transitions, and scope reports to selected modules after synthesis and place-and-route preparation.

cocotb 2.1.0 is a substantial verification tooling release with an experimental pytest plugin, Python 3.14 support, Verilator SAIF tracing support, Questa QIS/Qrun runner support, richer test controls such as xfail and skipif, and scheduler, callback, JUnit, and simulator-integration fixes.

OpenHW TV published Prof. David Harris and Dr. Rose Thompson's webinar introducing RISC-V System-on-Chip Design and its hands-on course material around CORE-V Wally. The recording highlights a practical open-source SoC platform spanning RV32I and RV64I, Linux-capable virtual memory, caches, branch prediction, RISC-V extensions, simulation, analysis, extension, and FPGA use.

lowRISC announced Peppermint as a new OpenTitan top level optimized for area-, cost-, and power-constrained SoCs such as wearables, IoT endnodes, and microcontrollers. The integrated Root of Trust is planned to handle secure boot, firmware updates, and cryptographic requests from the main SoC, with design work planned for H2 2026 and software plus verification completion in H1 2027.

RISC-V International published a RISER project snapshot on a microserver platform for European RISC-V cloud-server and accelerator prototyping. The article describes an FPGA-assisted standalone node that integrates the EPAC1.5 RISC-V vector-processor test chip with boot firmware, NVMe storage, and 100 Gbps Ethernet, and links the work to bring-up and use-case validation challenges.

CHIPS Alliance published the initial Caliptra 2.1 MCU Runtime SDK release, a Rust-based reference Root of Trust runtime built on Tock. The SDK includes reusable capsules, hardware-abstraction interfaces, reference drivers, userspace APIs, protocol stacks, reference applications, host tooling, and emulator plus FPGA reference platforms for SoC-specific integration.

The Python core development blog announced that RISC-V is now officially supported by CPython as a Tier 3 platform. The announcement credits community work, RISE-provided real RISC-V hardware for CPython buildbots, and ongoing plans to improve RISC-V CI, with PEP 11 listing riscv64-unknown-linux-gnu under Tier 3 support.

CHIPS Alliance published Caliptra firmware 2.0.3 as a combined runtime and FMC release. The release adds MCU runtime anchoring in the Caliptra-managed DPE chain, SoC manifest preamble DPE contexts, owner authorization manifest support, tagged DPE context SVN reporting, larger DMA image hashing, dynamic entropy_src power handling, staged subsystem OTP provisioning, and security/runtime fixes around DPE cache hardening, PAUSER validation, reserved firmware IDs, and PL0 authorization boundaries.

LLVM's CIRCT project released firtool 1.157.0 with ESI cosimulation build improvements for Verilator FST tracing, FIRRTL initial-value and inliner updates, Moore lowering fixes, ImportVerilog type checking, and circt-synth datapath simplifications.

RISC-V International profiled Ferrite Engineering's EDACrux suite for RISC-V chip design and verification. The article highlights WaveCrux, NetCrux, LintCrux, and SimCrux cross-probing, with WaveCrux using RVFI signals to inspect retired instructions and run consistency checks against the RISC-V ISA specification for cores such as Ibex, CVA6, PicoRV32, SERV, and VeeR.

Antmicro introduced Faultergeist, an open-source fault-injection framework for testing digital designs against single-event upset vulnerability in Verilator. The workflow generates fault campaigns with Weibull and Bendel cosmic-radiation models validated against irradiation data, then injects bit flips at simulation runtime through a VPI plugin.

CHIPS Alliance released Chisel 7.14.0 with a notable migration signal for hardware designers: implicit truncation is deprecated through firtool warnings, while new APIs add domain helpers, an LTL always operator, wide logical operators, Option support for Connectable, and an explicit truncating connection operator.

LLVM CIRCT published firtool 1.155.0 with hardware-compiler updates including aggregate-constant support in HW bitcast folding, broader LLHD loop-unrolling support, ESI runtime and channel work, Moore/SystemVerilog lowering fixes, FIRRTL domain and constant-expression updates, RTG effect-system additions, and BMC trace/counterexample handling.

Google announced that it formally joined the OpenROAD Initiative as a principal member, with Aaron Cunningham appointed to the ORI Governing Board. The announcement frames the membership around neutral open-source EDA stewardship, ecosystem growth, workforce development, CI/CD strengthening, PDK enablement, and improving the OpenROAD user experience.

Yosys 0.68 is a formal open EDA release that adds the symfpu and symfpu_convert passes, removes several legacy or superseded options from ABC, flowmap, synth, synth_ice40, and read_aiger flows, and includes compatibility fixes such as Radiant netlist handling.

lowRISC describes an I3C interface for OpenTitan Earl Grey 2, with SDR raw bitrates up to 12.5 Mbps and HDR-DDR up to 25 Mbps. These are raw bitrates, not effective payload throughput. The article also explains low-power operation and SCL drive control.

Tenstorrent published tt-metal v0.75.0 as the latest final release in its open AI accelerator stack, with broad LLK, Metalium, and TT-NN changes for Quasar and Blackhole, SFPU accuracy and tiny-tile work, trace and fabric improvements, fused MoE and SDPA fixes, and model bring-up across Llama, Qwen, Kimi, Gemma, and DeepSeek workloads.

OpenHW TV published PlanV Tech's webinar on open verification for RISC-V and high-assurance silicon. The session connects UVM support for Verilator, industrial environments such as CORE-V-VERIF, emerging formal verification frameworks, and end-to-end trust concerns spanning RTL verification, formally verified device drivers, and trusted embedded systems.

RISC-V International highlighted a two-phase extension-migration workflow that uses the RISC-V Unified Database as the source of truth, MCP-connected LLM tooling for conflict analysis and remapping proposals, and open hardware/software artifacts including packed-SIMD extensions, simulator support, GNU assembler integration, Zephyr runtime support, and RTL for more than 140 migrated instructions.

Antmicro announced that it has joined the OpenROAD Initiative after long-running contributions to the OpenROAD project, framing the move around transparent governance, open-source FPGA and ASIC tooling, architecture exploration, silicon prototyping, and reproducible RTL-to-GDSII flows for faster chip-design feedback.

CIRCT released firtool 1.154.0 with hardware-compiler updates including Arcilator stream printing and DLTI handling, circt-bmc support for verif.formal and verif.contract operations, ImportVerilog and Moore support for $readmemb/$readmemh, packed-struct bit-range fixes, and HWToLLVM union-buffer sizing through module DLTI.

CHIPS Alliance announced Qualcomm Technologies as a new Platinum Member, with Lu Dai joining the Governing Board and the alliance highlighting Qualcomm's SoC, verification, standards, and design-manufacturing flow expertise as support for open-source RTL, verification methodology, and automated hardware flows.

lowRISC published the OpenTitan Earl Grey 2 roadmap, positioning the next discrete hardware root of trust around optional CHERI memory safety, CNSA 2.0-aligned post-quantum cryptography accelerator work, a combined I3C controller/target, and area/power reductions while the design is upstreamed through H2 2026 and H1 2027.

Tenstorrent published tt-metal v0.74.0 as a final release after the RC stream, with LLK/Metalium optimizations for atanh, asinh, and acosh, TT-NN scalar divide-by-zero fixes, and model bring-up work for Llama 3.2 3B, Qwen3 32B, Llama 3.3 70B, Phi-4, and Gemma4 on the Tenstorrent stack.

Caliptra MCU SW released rom-sdk-2.1.0 as a platform-independent no_std RISC-V ROM library for Caliptra 2.1, adding OCP LOCK documentation, DOT and owner-key handling, field-entropy and fuse-layout guidance, MCU-side SVN anti-rollback, encrypted firmware boot support, ROM milestone hooks, and broader FPGA/reference-platform support.

CIRCT firtool 1.153.0 is a formal release with firtool verification-pass registration, Moore/SystemVerilog string-lowering fixes, ImportVerilog hierarchical-reference and foreach-loop support, ESI runtime/codegen fixes, Arc coroutine-lowering updates, and FIRRTL LowerLayers and LowerMemory improvements; 1.153.1 followed as a small patch release.

lowRISC announced Tampere University as an OpenTitan academic partner, bringing SoC Hub work in hardware security, RISC-V architecture, cryptographic acceleration, PQC implementation, side-channel analysis, fault injection, and open-source SoC integration into the secure-silicon coalition.

MLCommons introduced an Edge Agentic Inference benchmark for MLPerf Inference v6.1, targeting on-device multi-turn LLM workloads on a single edge accelerator with Qwen3.6-27B, BFCL v4 accuracy, recorded coding replay, and a July 31 submission deadline.

Yosys 0.67 now requires CMake 3.28, Clang 16 or GCC 13, moves SystemVerilog support to sv-elab on top of slang, adds working Microsoft Visual Studio builds including ABC, and expands passes such as check_mem, arith_tree, equiv_opt, sim, proc, and latch handling.

MLCommons described MLPerf Tiny v1.4 as an architecture-neutral benchmark for ultra-low-power AI, measuring accuracy, latency, and energy per inference across 25 system configurations from nine organizations, including Andes RISC-V configurations and accelerator-based submissions.

RISC-V International highlighted GAPses, an open wearable research platform using the GAP9 ultra-low-power RISC-V multicore processor for on-device EOG/EEG signal processing and CNN inference, converting eye-movement signals into BLE events without cloud compute.

lowRISC announced that AMI joined the OpenTitan project, adding firmware-security and manageability expertise to a coalition that already includes Fraunhofer, Google, Nuvoton, and Realtek around transparent open-source secure silicon.

Antmicro's Topwrap 0.7.0 update adds optimized component-based YAML syntax, initial clock/reset domain support with sanity checks, hierarchical SystemVerilog parsing into diagrams, GUI improvements, and planned Renode and IP-XACT integrations for SoC design flows.

LLVM CIRCT released firtool 1.152.0 with ImportVerilog and Moore simulation updates including fscanf/sscanf, timeformat, library-binding format specifiers, string-comparison lowering, Arc LowerProcesses work, and several FIRRTL inliner and dedup fixes.

RISC-V published a new ISA Manual snapshot built from commit f89d503. The official release notes call out a fix to the bit-manipulation reference pseudocode and link the full diff from the June 26 snapshot.

lowRISC announced the second MVP release of the CHERI Mocha Secure Enclave reference design. The subsystem SoC can boot CHERI Linux, adds secure-enclave IP blocks such as entropy, KMAC, ROM controller, SPI host, and debug support, and includes Genesys 2 board synthesis collateral.

Antmicro detailed a simulation-driven Coral NPU flow that embeds a RISC-V-based Coral NPU block into an NXP i.MX 8M Plus Renode Linux demo, uses RVV example payloads, and runs UVM-based Coral NPU DV under Verilator through upstreamed flow changes.

Antmicro described an OpenROAD resynthesis update that integrates mockturtle's extended mapper through a new resynth_emap command. In the published SKY130 jpeg_encoder example, multi-output mapping reduced area by roughly 10% after timing repair.

RISC-V published a new ISA Manual snapshot built from commit dc8bf2a. The release follows the June 23 snapshot and updates the Zkr example through RISC-V ISA Manual pull request 3227.

LLVM CIRCT published firtool 1.151.0. The release fixes invalid ESI connections from Unpack(pack()), addresses a FIRRTL inliner N-squared crash, lowers non-domain.define domain operands, adds Arc simulation-driver generation, extends the SV dialect with sv.fclose and sv.concat_str, supports sim.fmt.string printing in SimToSV, and fixes an O(NM) Comb extract-of-concat path.

Tenstorrent published TT-Metalium v0.73.1 as a final release for its open-source AI accelerator stack. The changelog includes MoE helper migration into C++ TT-NN, Gemma 4 performance and prefill/decode work, DeepSeek prefill and decode fixes, SDPA and KV-cache updates, Quasar LLK and firmware changes, Device 2.0 API migrations, fabric/dispatch improvements, and refreshed FW/KMD/SMI documentation.

lowRISC detailed an upstream OpenTitan ML-DSA implementation that uses OTBN, KMAC, SIMD-style arithmetic, and a formally verified masking accelerator to fit a first-order side-channel-hardened post-quantum signature flow into 16 KiB of instruction memory and 32 KiB of data memory.

RISC-V published a new ISA Manual snapshot from commit cc30642. The release clarifies that c.jal is only in XLEN=32 Zca, connects unprivileged and privileged cross-references, and fixes the Zvkt DIEL constant-time instruction list for vmslt[u].vv and vrsub.vi.

Apache TVM introduced TIRx, an open-source hardware-native DSL and compiler stack for ML kernels, shipping with the Apache TVM 0.25.0 Python package, documentation, a community kernel library, benchmarks, and course material for expert-written, agent-generated, and megakernel-style accelerator code.

CHIPS Alliance published Caliptra FW 2.0.2 as a combined runtime and FMC release for the 2.0 branch. It adds DPE SVN and crypto API work, DPE ML-DSA hybrid mode, attested CSR mailbox commands, ML-DSA/ECDH pairwise tests, richer firmware verification reporting, recovery capability updates, and fixes around production debug unlock, mailbox validation, AES-GCM GHASH state, FIPS marking, and shutdown zeroization.

CHIPS Alliance published Caliptra FW 2.1.1 as the latest combined runtime and FMC release. The 2.1 branch update adds SIGN_WITH_EXPORTED_MLDSA, chunked DPE certificates, initial activation handling, and more fw_info telemetry, while fixing debug-unlock mailbox behavior, ActivateFirmware authorization and bitmap handling, manifest metadata bounds, AES-GCM streaming GHASH state, runtime startup KAT coverage, ML-KEM/ML-DSA/ECDH pairwise tests, FIPS shutdown zeroization, and mailbox PAUSER checks.

Chipyard 1.14.0 is a broad RISC-V SoC generator release with AWS F2 support for FireSim, limited Chisel 7.13.0 support, modular lite builds, multichip and CTC improvements, Zephyr RTOS support, early Radiance/GPU integration, new FPGA/config examples, and updated Rocket Chip, BOOM, Shuttle, Saturn, Spike, Gemmini, and related submodules.

CIRCT published firtool 1.150.0 with substantial open EDA compiler updates, including ImportVerilog support for use-before-declare, builtins, DPI export declarations, plusargs, assertions, and declaration handling; FIRRTL lowering and domain fixes; Synth and comb lowering work; ESI runtime improvements; and Arc coroutine lowering.

RISC-V International interviewed SHD Group on its 2026 RISC-V Market Analysis, explaining a top-down/bottom-up model across nearly 60 applications, 12 device types per system, and more than 70 ecosystem interviews, with headline 2031 forecasts of 35.9 billion RISC-V SoC units and $318 billion in associated revenue.

Apache TVM v0.25.0 is a final release, not an RC, with broad compiler/runtime maintenance across Relax, frontend importers, TIR analysis and scheduling, runtime backends, and developer workflow updates since v0.24.0.

CHIPS Alliance published Caliptra ROM 2.0.3 for the 2.0 branch, adding SS_STRAP_GENERIC[2] entropy-source configuration and CTR_DRBG-AES-256 plus MLDSA-87 KAT coverage, while fixing ROM shutdown zeroization, CSRNG health-test behavior, production debug unlock binding, boot-failure reporting, and FIPS marking around hash-based ECDSA/LMS verification.

Antmicro benchmarked Gemma 4 variants on its open hardware NVIDIA Jetson AGX Thor baseboard, using the open-source Kenning framework with llama.cpp to generate performance reports for embedded edge-AI deployment.

Caliptra ROM 2.1.2 adds Stable Owner Key derivation from the HEK seed and gates fatal-error reporting on the recovery reset strap, with fixes for firmware verification after ICCM load, entropy and CSRNG setup, production debug unlock rejection, ROM shutdown zeroization, OCP LOCK key-ladder use of DOE, and identity root-key write locks.

CHIPS Alliance released a documentation-only Caliptra Subsystem 2.0.2 collateral update that explicitly leaves the RTL design unchanged, follows the Caliptra subsystem release checklist, drops the volatile PK hash lock from the spec, and cherry-picks documentation clarifications from main.

Antmicro described Host Controller support for the CHIPS Alliance open-source I3C Core, connecting the IP to Caliptra, Guineveer, the VeeR EL2 RISC-V core, and AXI-based SoC building blocks for more reusable open peripheral fabrics.

MLCommons released MLPerf Training v6.0 results with new DeepSeek V3 and GPT-OSS 20B sparse MoE benchmarks, reporting 95 unique systems across thirteen hardware accelerators and broader cloud/on-premise training submissions.

Tom's Hardware, citing The Information, reported that Qualcomm has discussed acquiring Tenstorrent at an $8 billion to $10 billion valuation. The report is unconfirmed, but it is relevant to the open hardware brief because Tenstorrent's RISC-V-based AI accelerators and data-center CPU IP sit at the center of the rumored rationale.

MLCommons released MLPerf Mobile v6.0 with generative AI tests for Llama 3.2 1B/3B and Llama 3.1 8B on Android devices, plus NPU-accelerated Llama 3.1 8B support on Snapdragon 8 Elite Gen 5 and updated MediaTek Dimensity 9500 and Samsung Exynos 2600 coverage.

FOSSi Foundation opened registration for ORConf 2026, scheduled for September 11-13 at the Zebrastraat event center in Ghent, Belgium, and co-located with FPL 2026. Talk submissions are open until August 16 for open-source silicon, EDA, FPGA, IP, and verification work.

OpenHW highlighted the inaugural RISC-V Ottawa launch meeting, with Mike Thompson covering the open-source RISC-V ecosystem, Frederic Desbiens covering open-source RTOSes, and attendees shaping local project directions.

OpenHW promoted the European Open Source Academy webinar on the open-source hardware ecosystem, featuring OpenHW Group, RISC-V International, CERN, and Barcelona Supercomputing Center voices on European open hardware collaboration and adoption.

CHIPS Alliance's OCP EMEA Summit recap highlights collaboration with the Open Compute Project around Caliptra, OpenPRoT, and Guineveer/VeeR EL2, including root-of-trust and open-source silicon infrastructure themes relevant to data-center security hardware.

OpenHW highlighted the RISC-V Summit Europe poster by Eclipse Foundation's Frederic Desbiens and 10xEngineers' Akif Ejaz on elevating Eclipse ThreadX into a first-class RTOS for RISC-V, connecting OpenHW's hardware focus with Eclipse's embedded software stack.

The Summit Europe 2026 poster program includes multiple CVA6-focused results: CVA6-CFI integrates the RISC-V Zicfiss and Zicfilp CFI extensions with 1.0% 22 nm FDX area overhead, while other posters cover CVA6-based secure boot with DICE and post-quantum cryptography, CAGE-V confidential computing, fault-tolerant CVA6, and CVA6-RT real-time extensions.

FOSSi's El Correo Libre Issue 98 says ODE4EC has begun as a three-year effort to strengthen Europe's open chip-design environment, with AMS, digital EDA, and productivity/verification projects for open EDA, open IP, and open PDK workflows.

lowRISC announced that Fraunhofer AISEC joined the OpenTitan coalition as an official security testing partner, adding independent physical attack evaluation, side-channel and fault-injection expertise, and assurance work around the Earl Grey secure microcontroller.

OpenHW Foundation joined RISC-V Summit Europe 2026 in Bologna as a Silver Sponsor, highlighting CVE2, CVE4, and CVA6 roadmap discussions, a CVA6 tech meetup covering Rigoletto and Tristan verification, the Unified Access Platform for EU RISC-V artifacts, and the newly announced CORE-ET silicon platform.

lowRISC and Realtek announced that Realtek has joined the OpenTitan project as a coalition partner and plans to use OpenTitan's platform-agnostic IP, firmware, and verification collateral to develop discrete hardware root-of-trust devices for networking, telecom, and IoT products.

Apache TVM FFI v0.1.12 adds reflection, Rust macro fixes, C-ABI-oriented AnyView changes, tensor API alignment, and ROCm/PyTorch DLPack loader fixes for the project's open ABI and framework-agnostic FFI layer for ML systems.

Antmicro announced that its open hardware baseboard for the NVIDIA Jetson Orin family is available for direct purchase through System Designer, with schematics, assets, customization paths, and AI edge-development use cases presented as part of the platform.

lowRISC published the first OpenTitan development bundle for Earl Grey 1.0.0, packaging FPGA bitstreams, a Verilated simulation binary, OpenTitanTool, HSMTool, test ROM, and FPGA ROM extension binaries for bring-up and integration work.

Ainekko announced that its CORE-ET Silicon Platform has been accepted as an OpenHW Foundation project. The platform combines many-core 64-bit RISC-V compute, MRAM-based memory, a scalable NoC, an architecture emulator, and open tooling for low-power edge AI inference.

MLCommons reported that Chakra has grown into a 40-plus-member effort with execution-trace support in PyTorch, NVIDIA NeMo, vLLM, ASTRA-sim, and commercial simulators, giving AI hardware and infrastructure teams a more portable way to benchmark and co-design training and inference systems.

Fraunhofer AISEC joined the OpenHW Foundation and described work on a secure SoC built around the RISC-V CVA6 core and OpenTitan root-of-trust platform, with GyroidOS already running on a CVA6 FPGA reference platform.

CHIPS Alliance's Latch-Up 2026 recap packages technical updates on SV Tools, UVM and four-state logic work in Verilator, VeeR/Guineveer open-source SoC flows, and IHP open PDK and MPW progress.

Antmicro connected NVIDIA's Jetson Yocto support with its own open source hardware baseboards, meta-antmicro Yocto layers, RDFM OTA and fleet management, Kenning AI benchmarking, and Protoplaster factory testing stack for reproducible edge-AI product development.

Chisel v7.13.0 adds a ChiselTest compatibility layer for Chisel 7, debug intrinsics for Chisel type metadata, and bumps the FIRRTL backend to 7.0.0 while carrying several core fixes and documentation updates.

Yosys 0.66 adds the lattice_dsp_nexus pass for Lattice Nexus DSP inference, extends synth_gatemate with a scopename option propagated to flatten, and moves the project baseline toward C++20 with a future CMake migration planned.

The latest CIRCT firtool release adds lower-to-core support for firrtl.fprintf, several SimToSV lowering fixes, larger-than-64-bit integral support in the ESI runtime, Windows cosim improvements, and new synthesis and equivalence-checking updates.

lowRISC outlined how OpenTitan validates side-channel and fault-injection countermeasures before tape-out, combining open-source tooling such as CocoAlma and PROLEAD with formal and simulation-based flows to catch vulnerabilities earlier in the security lifecycle.

A KTH, Lawrence Livermore, and Barcelona Supercomputing Center paper uses RVV 1.0 microbenchmarks on BananaPi-F3 and other RISC-V vector hardware to compare GCC 15 and Clang 21, finding GCC more stable across most scientific and ML proxy workloads while exposing remaining compiler and profiling gaps.

Antmicro detailed a runtime force-tracking implementation for Verilator that supports conditional and overlapping SystemVerilog force/release statements more closely aligned with IEEE 1800-2023, with the work included in Verilator 5.048.

lowRISC announced that Real Intent has joined the OpenTitan coalition as an official tools partner, adding access to static sign-off tools for hardware security, linting, clock-domain crossing, and reset-domain crossing checks.

lowRISC announced that Cadence has joined the OpenTitan coalition as an official tools partner, bringing enterprise EDA support across verification, formal analysis, synthesis, and physical implementation for OpenTitan designs.

Yosys 0.65 adds an arith_tree pass for converting add/sub/macc chains to carry-save adder trees, removes the share -force option, and improves read_verilog support for positional assignment patterns for unpacked arrays.

Apache TVM v0.24.0 bundles broad fixes across code generation and runtime backends while adding fresh architecture documentation and modernizing developer workflows with uv-based Python dependency management and a GitHub Actions lint path.

RISC-V International introduced the Ratified Specifications Library, a consolidated site for ratified RISC-V specifications in HTML and PDF formats, designed to replace scattered repository and draft-page discovery paths.

Antmicro described a genetic-algorithm-based local resynthesis strategy for OpenROAD that complements simulated annealing, exposing tunable search parameters and showing cases where targeted tuning improves timing and power on selected OpenROAD-flow-scripts designs.

MLCommons described GPT-OSS 20B, a sparse Mixture-of-Experts pretraining benchmark for MLPerf Training v6.0 designed to run on a single 8-GPU node while testing MoE routing, sparse computation, and hardware/software training efficiency.

Antmicro expanded simulation-based testing for Google's ChromiumOS fingerprint firmware module by adding Renode support for an Egis ET171 platform based on the RISC-V Andes D25F core and Zephyr RTOS.

FOSSi published Mike Thompson's Latch-Up 2026 talk, "RISC-V in Space (The Canadian version)". The talk describes a Canadian effort with the University of Saskatchewan and collaborators to fabricate an open-source RISC-V chip, radiation-harden the design, and build a space-ready chip; the MCU is based on OpenHW Foundation's CV32E40P.

Antmicro outlined an experimental four-state logic implementation for Verilator under a --fourstate flag, using paired two-state variables internally so open-source ASIC and FPGA teams can debug X and Z behavior with fewer blind spots.

OCP announced newly approved AI infrastructure contributions spanning Open Rack Wide, Ethernet-based AI cluster reference architectures, facility power and telemetry work, and the Foundation Chiplet System Architecture, extending its open 'chip to grid' roadmap for AI deployments.

RISC-V International highlighted a community pipeline that brought Docker v29 to RISC-V64 within six days of release using native RISC-V hardware builds for Docker Engine, CLI, Compose, and Buildx.

lowRISC detailed OpenTitan's open physical security testing framework, which coordinates side-channel and fault-injection evaluation from FPGA-based pre-silicon analysis through post-silicon certification and is wired into CI to catch regressions in the security validation flow.

ACT 4.0 is a major update to the RISC-V Architecture Certification Test suite, replacing the older riscof/riscv-ctg/riscv-isac/riscv-config flow with a new Python-based flow.

Antmicro described an optional dual-core lockstep feature for VeeR EL2, including shadow-core behavior, multibit control encoding, error reporting, and cocotb/PyUVM-based verification.

OCP described Foundation Chiplet System Architecture as a CPU-architecture-neutral framework for chiplet systems, defining common chiplet classes and hardware/fabric-level interface expectations under the Open Chiplet Economy initiative.

CHIPS Alliance introduced the SV Tools Project to improve visibility and support for open-source SystemVerilog and UVM tooling, including sv-tests, Verible, Synlig, and RISCV-DV.

RISC-V International featured Thales' work on a cycle-based Python performance model for CVA6, used to guide a dual-issue CVA6 implementation and improve CoreMark/MHz with modest power and area overhead.

MLCommons detailed new MLPerf Inference v6.0 workloads for GPT-OSS 120B and a latency-constrained DeepSeek-R1 interactive scenario, including speculative decoding requirements and reference implementation links.

Caliptra RTL v2.1.2 is a patch release for Caliptra 2.1 RTL, including AES countermeasure and Key Vault hardening plus a future-use ML-KEM Key Vault endianness fix.

CHIPS Alliance described an open digital design flow using Topwrap and Guineveer, a RISC-V reference SoC based on the VeeR EL2 core, for modular and reusable SoC construction.

OpenHW announced the Unified RISC-V IP Access Platform as part of TRISTAN, positioning it as a unified source for verified, industry-ready RISC-V components and related open-source artifacts.

The OpenHW CVA6 repository published CV32A60X 6.0.0 as a dedicated configuration release, adding an OBI-based pipeline hierarchy, removing caches and PMP entries, and improving coverage, lint results, and configuration documentation.

Gemmini v0.7.1 is an incremental accelerator release that adds rectangular convolution support, ships new Timeloop configurations, improves area for runtime-configurable dataflows, and speeds up build and elaboration time.